Debugging apparatus and method

ABSTRACT

A debugging apparatus includes: a processor core operated by a program stored in a program memory to read a data stored in a data memory or write a data; a debugger controller for performing a debugging on the processor core upon receipt of a command from a host computer and outputting a data break point address; and a memory break controller for observing an address of a data memory used by the processor core, recognizing an address as a break point address to output a break signal to the debugger controller and the processor core to suspend the operation of the processor core, when the address is sensed to be identical, and transmitting a corresponding address and data to the host computer through the debugger controller. Since an address and a data of a specific data memory are monitored to recognize a data flow and change of the specific address, an error that an erroneous calculation is inputted a during processing or a data memory is erroneously assigned is quickly sensed. Thus, a time and an expense for a debugging operation can be much saved. In addition, by adding a data debugging method to the conventional program debugging method, a program development environment is set similar to an environment substantially operated by the processor. Thus, a time and an expense for developing a program can be also saved.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a debugging apparatus andmethod, and more particularly, to a debugging apparatus that is capableof recognizing a data conversion state in a specific memory by observinga change and flow of a specific data of a memory and performing adebugging, and its method.

[0003] 2. Description of the Background Art

[0004] In general, a debugging apparatus, detecting an error generatedto a program inputted to a microprocessor, includes a host computer anda microprocessor unit (MPU).

[0005] In the debugging apparatus, when the host computer selects aspecific address of a program memory in the MPU as a break point, theMPU monitors the processor while the processor is being operated, andwhen the specific address of the program memory is identical to thememory address selected as the break point, the MPU recognizes theselected memory address as a break point and discontinues the operationof the processor and the host computer observes a flow of a program andperforms a debugging on the program.

[0006]FIG. 1 is a schematic block diagram of the debugging apparatus inaccordance with a conventional art.

[0007] As shown in FIG. 1, the debugging apparatus includes: a hostcomputer 1 for selecting a specific address of a memory as a break pointand performing a debugging; a debugger controller 2 for receiving acontrol command from the host computer 1 and outputting a break enablesignal and a break point address; a processor core 4 being operated uponreceiving a control signal from the debugger controller 2; a programmemory 5 for storing a program of the processor core 4; a data memory 6for storing a data of the processor core 4; and a break point sensingunit 3 for receiving the break enable signal and the break point addressfrom the debugger controller 2, observing an address of the programmemory 5 being executed in the processor core 4, and recognizing anaddress as a debugger break point and outputting a break signal to thedebugger controller 2 if the address is sensed to be identical to theinputted break point address.

[0008] The operation of the debugging apparatus constructed as describedabove will now be explained.

[0009] When the processor is switched to a debugging mode, the hostcomputer 1 outputs a processor core stop signal and a break pointaddress to the debugger controller 2, for debugging.

[0010] The debugger controller 2 outputs a stop signal to the processorcore 4 to suspend the processor core 4, and outputs a break pointaddress and a break enable signal to the break point sensing unit 3.

[0011] When the break point sensing unit 3 stores a program address thatthe processor core 4 wants to suspend in the program memory, that is,stores a break point address, the host computer 1 operates the processorcore 4 in the order of programs stored in the program memory 5.

[0012] While the processor core 4 is operated in the program order, thebreak point sensing unit 3 observes a program address outputted to theprocessor core 4.

[0013] Subsequently, when the break point sensing unit 3 detects anaddress of the same program memory 5 as that of the stored programaddress, it outputs a break signal to the debugger controller 2.

[0014] The debugger controller 2 suspends the operation of the processorcore 4 according to the break signal inputted from the break pointsensing unit 3 and shifts a debugging control right to the host computer1, so that the host computer 1 may perform a debugging operation.

[0015] However, in the debugging method, since an operation isdetermined by an address of a specific program memory among thesequential programs, it is not possible to recognize a data flowaccording to a data memory. Thus, in case where an error occurs by adata, much time and expense is taken for debugging.

[0016] In addition, in case of creating a program, since the state of adata is hardly recognized, an error occurs in a data memory allocationamount. In addition, in case of reading out a wrong data in acalculating process, an erroneous result value is outputted only tocause a malfunction to a system.

SUMMARY OF THE INVENTION

[0017] Therefore, an object of the present invention is to provide adebugging apparatus and method that is capable of saving a time and anexpense in performing a debugging operation by recognizing a datatransition state in a specific data memory by observing a change stateand flow of an address and a data of the specific data memory in a datamemory.

[0018] To achieve these and other advantages and in accordance with thepurpose of the present invention, as embodied and broadly describedherein, there is provided a debugging apparatus including: a processorcore operated by a program stored in a program memory to read a datastored in a data memory or write a data; a debugger controller forperforming a debugging on the processor core upon receipt of a commandfrom a host computer and outputting a data break point address; and amemory break controller for observing an address of a data memory usedby the processor core, recognizing an address as a break point addressto output a break signal to the debugger controller and the processorcore to suspend the operation of the processor core, when the address issensed to be identical, and transmitting a corresponding address anddata to the host computer through the debugger controller.

[0019] To achieve the above objects, there is further provided adebugging method including the steps of: outputting an address of a datamemory to be observed, that is a break point address and a break enablesignal, when a processor is switched to a debugging mode; storing theoutputted break point address, and operating the processor in a generaloperation state; comparing the stored break point address and theaddress of the data memory currently used by the processor core, whilethe process is being operated; outputting a break signal to suspend theprocess core, if the address of the data memory currently used by theprocessor core and the stored break point address are identical to eachother; and suspending the processor core by the outputted break signaland switching the processor to a debugging mode to debug the program.

[0020] The foregoing and other objects, features, aspects and advantagesof the present invention will become more apparent from the followingdetailed description of the present invention when taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which are included to provide afurther understanding of the invention and are incorporated in andconstitute a part of this specification, illustrate embodiments of theinvention and together with the description serve to explain theprinciples of the invention.

[0022] In the drawings:

[0023]FIG. 1 is a schematic block diagram showing a debugging apparatusin accordance with a conventional art;

[0024]FIG. 2 is a schematic block diagram showing a debugging apparatusin accordance with a preferred embodiment of the present invention;

[0025]FIG. 3 is a detailed block diagram showing a memory breakcontroller of FIG. 2 in accordance with the preferred embodiment of thepresent invention;

[0026]FIG. 4 is a schematic block diagram showing the structure of amemory break control register of FIG. 3 in accordance with the preferredembodiment of the present invention; and

[0027]FIG. 5 is a flow chart of a debugging method in accordance withthe preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] Reference will now be made in detail to the preferred embodimentsof the present invention, examples of which are illustrated in theaccompanying drawings.

[0029]FIG. 2 is a schematic block diagram showing a debugging apparatusin accordance with a preferred embodiment of the present invention.

[0030] As shown in FIG. 2, a debugging apparatus of the presentinvention includes a host computer 10 for assigning a break pointaddress and controlling a debugging operation; a debugger controller 20for outputting a control signal to control a processor outputted fromthe host computer 10, a break point address and a break enable signal; aprogram memory 60 for storing a program to operate a processor core 40(to be described); a processor core 40 being operated by the controlsignal outputted from the debugger controller 20 and the program storedin the program memory 60, and outputting a data generated accordingly; adata memory 70 for storing a data outputted from the processor core 40;a break point sensing unit 30 for observing an address of the programmemory 60 used by the processor core 40, and recognizing an address as adebugger break point and transmitting a break signal to the debuggercontroller 20, if the address is sensed to be identical to the breakpoint address outputted from the debugger controller 20; and a memorybreak controller 50 for observing an address and a data of the datamemory 70 used by the processor core 40, and transmitting a break signalto the debugger controller 20 and the processor core 40 to suspend anoperation of the processor core 40, transmitting the sensed address andits corresponding data to the host computer 10 through the debuggercontroller 20, and activating an operation of the processor core 40 totransmit the address and data of the data memory used in the processorcore 40 to the host computer 10 through the debugger controller 20 untila break signal is outputted again, when the same address as the breakaddress outputted from the debugger controller 20 is sensed.

[0031] The host computer 10 recognizes a data flow and change accordingto the address and the data outputted from the memory break controller50.

[0032] The construction of the memory break controller of the debuggingapparatus will now be described with reference to FIG. 3.

[0033]FIG. 3 is a detailed block diagram showing a memory breakcontroller of FIG. 2 in accordance with the preferred embodiment of thepresent invention.

[0034] As shown in FIG. 3, the memory break controller 50 includes amemory break control register 51 being activated by a control signal anda break point address signal outputted from the debugger controller 20and observing a data change of the processor core 40; an addressregister (AR) 52 for storing the break point address outputted from thememory break control register 51; an address comparator (AC) 53 forcomparing the address currently outputted from the data memory 70 andthe break point address stored in the address register 52; a dataregister (DR) 54 for storing a data of the break point address stored inthe address register 52; and a data comparator (DC) 55 for comparing thedata of the address outputted from the data memory 70 and the data valueof the break point address stored in the data register 54.

[0035] The construction of the memory break control register 51 will nowbe described with reference to FIG. 4.

[0036]FIG. 4 is a schematic block diagram showing the structure of amemory break control register of FIG. 3 in accordance with the preferredembodiment of the present invention.

[0037] As shown in FIG. 4, the memory break control register 51includes: a memory break enable flag (MBEF) 51-1 for activating thememory break controller 50; a data check flag (DCF) 51-2 for sensing anaddress of the data memory which is identical to the break point addressstored in the address register 52 and being enabled when the data of thecorresponding address is outputted; and an address trace check flag(ACF) 51-3 assigning an initial break point address, being enabled whena content of the break point address is read during the processingprocedure, and outputting the content of the data and the addresses ofevery memory read or written from or into the processor until thecontent of the break address is updated.

[0038] The operation of the debugging operation constructed as describedabove will now be explained with reference to FIG. 5.

[0039]FIG. 5 is a flow chart of a debugging method in accordance withthe preferred embodiment of the present invention.

[0040] As shown in FIG. 5, while the processor in the host computer 10is being operation, when it is switched to a debugger mode, the hostcomputer 10 disables the debugger mode, so that the host computer sets astart position of a debugger mode program as a start position of theprocessor and outputs an initialization control signal and an address ofthe data memory to be observed, that is, a break point address, to thedebugger controller 20.

[0041] According to the control signal and the break point addressoutputted from the host computer 10, the debugger controller 20 outputsthe control signal, the break point address and the break enable signalto the memory break controller 50 and the break point sensing unit 30.

[0042] The break point sensing unit 30 receives and stores the breakenable signal and the break point address.

[0043] According to the inputted break enable signal, the memory breakcontrol register 51 of the memory break controller 50 enables a memorybreak enable flag as ‘1’ and disables a data check flag and an addresstrack flag as ‘0’ (step S10), thereby initializing the processor.

[0044] The address register 52 of the memory break controller 50 storesthe inputted break point address (step S11).

[0045] After completing the process, the host computer 10 operates theprocessor core 40 according to programs stored in the program memory 60.

[0046] When the processor core 40 is operated according to the programsequentially stored in the program memory, the break point sensing unit30 monitors whether the break point address stored in the processor core40 and the address of the program memory 60 used by the processor core40 are identical to each other.

[0047] The address comparator 53 of the memory break controller 50compares the address of the data memory 70 used by the processor core 40and the break point address (step S12).

[0048] Upon comparison, if the address of the data memory 70 read fromthe processor core 40 and the break point address stored in the addressregister 52 are identical to each other, that is, if the addresscomparator 53 is enabled, the address comparator 53 outputs an accordsignal to the debugger controller 20.

[0049] The debugger controller 20 judges whether the processor core 40is reading a data for the corresponding address of the data memory 70 orwriting a data to the address of the data memory 70 (step S14).

[0050] According to judgement result, in case that the processor core 40writes a data in the data memory 70, the debugger controller 20 enablesa data check flag (51-2) of the memory break control register 51 (stepS18) and outputs a break signal for suspending execution of the programof the processor core 40 to the the processor core 40 (step S20), so asto discontinue the operation of the processor core.

[0051] Meanwhile, in case that the processor core 40 reads a data of anaddress of the corresponding data memory 70, the debugger controller 20enables an address trace check flag (ACF) 51-3 and a data check flag(CDF) 51-2 of the memory break control register 51 (step S15).

[0052] The data of a specific address of the data memory (70) read bythe processor core 40 has an arithmetic and logical operation relationwith a data value of a difference address or a correlation with aspecific address of the data memory 70.

[0053] Accordingly, in case that a data of a specific address is read,when the address trace check flag 51-3 and the data check flag 51-2 areenabled, the address comparator 53 compares the specific address and thebreak point address (step S16).

[0054] When the break point address stored in the address register 52and the address of the data memory 70 are identical to each other, theaddress comparator 53 transmits an accord signal to the debuggercontroller 30.

[0055] If, however, the break point address and the address of the datamemory are not identical to each other, that is, if the value (AC) ofthe address comparator 53 is not ‘1’, since the break point address andthe address to be observed are different arithmetically and logically,the address comparator 53 and the data comparator 55 transmit the sensedaddress and data of the corresponding data memory to the host computer10 through the debugger controller 20, for a debugging operation. (stepS17).

[0056] Meanwhile, when the address comparator 53 is enabled, it meansthat the previously read address to be observed is used, the debuggercontroller 20 determines whether the processor core 40 is reading a dataof the address to be observed of the data memory 70 or a data value iswriting into the address to be observed (step S19).

[0057] In case that a data of the address to be observed of the datamemory 70 is being read, since it is the previously read address to beobserved, it returns to the step in which the address comparator 53 ofthe memory break controller 50 compares the read address and the breakpoint address and determines whether the read address is identical tothe break point address stored in the address register 52 (step S16).

[0058] Meanwhile, in case that a data value is being written in aaddress to be observed, since it means that a result value according toan arithmetic operation is being written in the previously read addressto be observed, the memory break controller 50 outputs a break signal tothe debugger controller 20 and the processor core 40 (step S20), inorder to discontinue the processor core 40.

[0059] Upon receiving the break signal, the debugger controller 20outputs a signal allowing the host computer 10 to start a debuggingoperation. The host computer 10 performs a debugging operation accordingto the outputted signal.

[0060] Meanwhile, the address to be observed and the address comparisonresult of the data memory currently used by the processor core 40 aredifferent to each other (step S12), the memory break controller 50outputs the address and data of the data memory 70 currently read by theprocessor core 40 to the host computer 10.

[0061] Subsequently, the address comparator 53 repeats from the step forcomparing the address of the next data memory 70 used by the processorcore 40.

[0062] The operation of the debugging apparatus as described above willnow be explained in detail by taking the following program as anexample.

A0=a  (1)

A1=b  (2)

A2=c  (3)

A2=A2+(A1*A2)  (4)

[0063] wherein A0, A1 and A2 are addresses of the data memory.

[0064] In the program constructed as described above, the host computer10 designates a address to be observed as A2 and executes the program ina debug mode.

[0065] The address comparator 53 executes a debugging while comparingA2, the address to be observed, and the currently used address, and whenthe address comparator 53 reads a data value ‘c’ corresponding to A2, itsenses A2 as an address to be observed.

[0066] When the address comparator 53 senses A2, the memory breakcontrol register 51 outputs a break signal to the processor core 40 inorder to discontinue the operation, and determines whether A2 of formula(3) is for reading or writing.

[0067] Upon determining, if A2 is for reading, the memory break controlregister 51 transmits the A2 address and the data value ‘c’ to the hostcomputer 10.

[0068] In case of executing continuously, the memory break controller 50reads A2, so that addresses of every memory related until the next A2value is written and their contents are outputted. That is, the addresscomparator 53 continuously executes the processor, stops at A2 of theformula (4), and compares A0, A1 and A2 with A2, the address to beobserved.

[0069] After the address comparator 53 first compares A0 and A1 with theaddress to be observed A2, since A0 and A1 are not identical to theaddress to be observed, the address comparator 53 transmits acorresponding address and data value to the host computer 10 andcompares A2 of the right side of the formula (4) with the address to beobserved.

[0070] Wince A2 is identical to the address to be observed, the memorybreak control register 51 determines whether it is reading or writing.

[0071] In this respect, A2 presented in the formula (3) is an addresswhich has been read in the previous process, it goes to the nextaddress.

[0072] Subsequently, after the right side of A2 of the formula (4) iscompared, the left side is compared. In this respect, after A2 issensed, it is determined whether it is reading or writing.

[0073] Since A2 of the formula (4) is for writing, the memory breakcontroller 50 outputs a break signal to the debugger controller 20 andthe processor core 40 to suspend the operation of the processor core 40.

[0074] The debugger controller 20 outputs a debugging mode switch signalto the host computer 10 by the inputted break signal.

[0075] Upon receiving the debugging mode switch signal from the debuggercontroller 20, the host computer 10 operates A2 by the previouslytransmitted address and data and updates A2 of the data memory to theoperated value.

[0076] In case that a data constructed with arrangement in the addressregister 52 is observed, the host computer 10 designates a break pointaddress as an uppermost address and a lowermost address of anarrangement of the address register 52 of the memory break controller50.

[0077] The address register 52 stores the uppermost address andlowermost address of the arrangement of the data register 54, and sets aspace for storing a data of the arrangement of the data register 54.

[0078] The address comparator 53 compares the range of the arrangementstored in the address register and the break point address and senses anaddress of the data memory corresponding to the range of thearrangement. The following operation is performed in the same manner asthe case of observing one data.

[0079] As so far described, the debugging apparatus and method of thepresent invention has the following advantages.

[0080] That is, for example, in a debugging operation, since an addressand a data of a specific data memory are monitored to recognize a dataflow and change of the specific address, an error that an erroneouscalculation is inputted a during processing or a data memory iserroneously assigned is quickly sensed. Thus, a time and an expense fora debugging operation can be much saved.

[0081] In addition, by adding a data debugging method to theconventional program debugging method, a program development environmentis set similar to an environment that the processor is substantiallyoperated. Thus, a time and an expense for developing a program can bealso saved.

[0082] As the present invention may be embodied in several forms withoutdeparting from the spirit or essential characteristics thereof, itshould also be understood that the above-described embodiments are notlimited by any of the details of the foregoing description, unlessotherwise specified, but rather should be construed broadly within itsspirit and scope as defined in the appended claims, and therefore allchanges and modifications that fall within the meets and bounds of theclaims, or equivalence of such meets and bounds are therefore intendedto be embraced by the appended claims.

What is claimed is:
 1. A debugging apparatus comprising: a processorcore operated by a program stored in a program memory to read a datastored in a data memory or write a data; a debugger controller forperforming a debugging on the processor core upon receipt of a commandfrom a host computer and outputting a data break point address; and amemory break controller for observing an address of a data memory usedby the processor core, recognizing an address as a break point addressto output a break signal to the debugger controller and the processorcore to suspend the operation of the processor core, when the address issensed to be identical, and transmitting a corresponding address anddata to the host computer through the debugger controller.
 2. Theapparatus of claim 1, wherein the data memory stores a data valueoutputted from the processor core.
 3. The apparatus of claim 1, whereinthe memory break controller transmits an address and a data recognizedas a break point, activates an operation of the processor core, andoutputs the used address and the data of the data memory to the hostcomputer through the debugger controller until a break signal isoutputted again.
 4. The apparatus of claim 3, wherein the host computerrecognizes a data flow and change by the address and the data outputtedfrom the memory break controller.
 5. The apparatus of claim 1, whereinthe memory break controller comprises: a memory break control registerbeing activated by the break point address and the control signalinputted from the debugger controller; an address register for storingthe break point address inputted from the memory break control register;an address comparator for comparing the address of the data memorycurrently used by the processor core and the break point address storedin the address register; a data register for storing the data of thebreak point address stored in the address register; and a datacomparator for comparing the data of the current address outputted fromthe data memory and the data of the break point address stored in thedata register.
 6. The apparatus of claim 5, wherein the memory breakcontrol register comprises: a memory break enable flag for activatingthe memory break controller; a data check flag for sensing an address ofthe data memory which is identical to the break point address stored inthe address register, and being enabled when the content of the data ofthe sensed address is outputted; and an address trace check flag forbeing enabled when the content of the address of the data memory whichis identical to the break point address stored in the address registeris outputted.
 7. The apparatus of claim 6, wherein when the addresstrace check flag is enabled, it outputs addresses and data of everymemory which are read from or written in the processor core before thecontent of the break address is updated.
 8. A debugging apparatus forinforming a data transition state, comprising: a debugger controller foroutputting a control signal for performing a debugging, a memory breakpoint address, and a break enable signal; a processor core beingactivated by the control signal outputted from the debugger controller,and reading a data stored in a data memory or writing a data; a memorybreak control register being activated by the break point address andthe control signal inputted from the debugger controller; an addressregister for storing the break point address inputted from the memorybreak control register; an address comparator for comparing the addressof the data memory which is currently used by the processor and thebreak point address stored in the address register; a data register forstoring the data of the break point address stored in the addressregister; and a data comparator for comparing the data of the currentaddress outputted from the data memory and the data of the break pointaddress stored in the data register.
 9. A debugging method comprisingthe steps of: outputting an address of a data memory to be observed,that is a break point address and a break enable signal, when aprocessor is switched to a debugging mode; storing the outputted breakpoint address, and operating the processor in a general operation state;comparing the stored break point address and the address of the datamemory currently used by the processor core, while the process is beingoperated; outputting a break signal to suspend the process core, if theaddress of the data memory currently used by the processor core and thestored break point address are identical to each other; and suspendingthe processor core by the outputted break signal and switching theprocessor to a debugging mode to debug the program.
 10. The method ofclaim 9, wherein in the step of operating a processor, a memory breakenable flag of a memory break controller is enabled according to anoutputted break enable signal, and a data check flag and an addresscheck flag are disabled, in order to initialize the processor, and thenthe break point address is stored.
 11. The method of claim 9, whereinthe step of outputting a break signal comprises: a step in which when anaddress of the data memory currently used by the processor core and thestored break point address are identical to each other, it is determinedwhether the processor reads the data stored in the corresponding addressor writes a data; a step in which, in case of reading a data, theaddress trace check flag and the data check flag of the memory breakcontrol register are enabled; a step in which the corresponding addressof the data memory and the stored break point address are comparedagain; and a step in which, if the corresponding address of the datamemory and the break point address are not identical to each other, thecorresponding address and data of the data memory are transmitted to thehost computer.
 12. The method of claim 11, wherein the step of comparingaddress comprises: a step in which, if the corresponding address of thedata memory and the break point address are identical to each other, itis determined whether the processor reads a data stored in the datamemory of the corresponding address or writes a data in the data memoryof the corresponding address; and a step in which, in case of writing adata, the data check flag of the memory break controller is enabled anda break signal for suspending the processor core is outputted.
 13. Themethod of claim 12, wherein, in case of reading a data upon judgement,an address of the next data memory to be used by the processor core andthe break point address are compared.
 14. The method of claim 11,wherein, in case of writing a data in the judging step, the data checkflag of the memory break controller is set and the operation of theprocessor core is discontinued.
 15. The method of claim 9, wherein, inthe step of outputting a break signal, when the operation of theprocessor core is suspended by the break signal, the address and data ofthe corresponding data memory are transmitted, and then the operation ofthe processor core is activated to output an address and a data of thedata memory used by the processor core until a break signal is outputtedagain.
 16. A debugging method for informing a data transition state,comprising: a step in which when a processor is switched into adebugging mode, an address of a data memory to be observed, that is, abreak point address, and a break enable signal are outputted; a step inwhich the outputted break point address is stored; a step in which thestored break point address and an address of a data memory currentlyused by a processor core are compared; a step in which, when the addressof the data memory currently used by the processor core and the storedbreak point address are identical to each other, it is determinedwhether the processor core reads a data stored in the correspondingaddress or writes a data; a step in which, in case of writing a data ina corresponding address, a data check flag of a memory break controlleris enabled and a break signal for suspending the processor core isoutputted; a step in which, when the processor core is suspended by theoutputted break signal, the address and the data of the correspondingdata memory are outputted; and a step in which the operation of theprocessor core is activated and the address and the data of the datamemory used by the processor are outputted until a break signal isoutputted again.
 17. The method of claim 16, wherein, in case of readinga data upon judgement, an address of the next data memory used by theprocessor core and the break point address are compared.